This invention relates to integrated circuits and, more particularly, to pipelined interconnect circuitry with double data rate interconnections on an integrated circuit.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which have led to performance increases. However, more recent technology nodes have seen a significant slow-down in the reduction of delays (i.e., a slow-down in the performance increase).
To further increase the performance, solutions such as register pipelining have been proposed, where additional registers are inserted between synchronous elements, thereby increasing latency for the benefit of increased clock frequencies and throughput. However, performing register pipelining often involves spending significant time and effort because several iterations of locating performance bottlenecks, inserting and removing registers, and compiling the modified integrated circuit design are usually required.
Situations frequently arise where a register pipelined integrated circuit design still exhibits an unsatisfactory performance after many iterations of inserting and removing registers because synchronous elements are placed far from each other and existing routing architectures do not support a high speed connection across the integrated circuit in an efficient manner.